In general, voltages supplied to a semiconductor memory device from outside a memory chip include a first external voltage VDD and a second external voltage VDDQ. FIG. 1 is a schematic block diagram of a conventional semiconductor memory device. As shown in FIG. 1, a semiconductor memory device 10 includes power pins 11 and 12, an internal voltage generator 13, a memory cell array 14, a peripheral circuit 15, and an output driver 17. The peripheral circuit 15 includes a delay locked loop (DLL) 16. The first external voltage VDD is supplied to the power pin 11, and the second external voltage VDDQ is supplied to the power pin 12.
The first external voltage VDD is supplied to the internal voltage generator 13 and the peripheral circuit 15 as a supply voltage. The internal voltage generator 13 generates an internal voltage by using the first external voltage VDD and supplies the generated internal voltage to the memory cell array 14 and the peripheral circuit 15. The second external voltage VDDQ is supplied to only the output driver 17.
Different supply voltages are provided to internal circuits of the semiconductor memory device 10 and the output driver 17 as discussed below with reference to FIG. 2. FIG. 2 shows a data input/output buffer of a conventional semiconductor memory device connected to a data input/output buffer of a controller on a printed circuit board (PCB). As shown in FIG. 2, an input/output buffer 21 of a memory chip 20 and an input/output buffer 41 of a controller chip 40 are connected with each other through a circuit pattern 31 on a printed circuit board (PCB) 30. The input/output buffer 21 includes an output driver 22 and an input receiver 23. The input/output buffer 41 includes an output driver 42 and an input receiver 43. Here, the output driver 22 has an output load including the resistance of the circuit pattern 31 on the PCB 30, a gate capacitance of the input receiver 43, and a junction capacitance of the output driver 42. Since the output load outside the memory chip 20 is greater than the load inside the memory chip 20, power consumption of the output driver 22 increases.
When voltage levels of a plurality of output data change at the same time, a simultaneous switching output (SSO) noise is generated due to a parasitic inductance of the power pin 12 of FIG. 1, which may cause a change in the level of the second external voltage VDDQ. Since the second external voltage VDDQ may include a large amount of noise, it is preferable that the second external voltage VDDQ is not used in the peripheral circuit 15 of the semiconductor memory device 10, particularly not in the DLL 16, which, typically, requires a very fine operation. Thus, different supply voltages are applied to the peripheral circuit 15 of the semiconductor memory device 10 and the output driver 17.
There have been increasing efforts to decrease the level of the second external voltage VDDQ, thereby reducing power consumption. The power consumption can also be reduced by decreasing the levels of both the second external voltage VDDQ and the first external voltage VDD. However, since the operating speed of the memory chip 20 is affected by the first external voltage VDD, it is desirable that only the level of the second external voltage VDDQ is reduced.
As seen in FIG. 1, The second external voltage VDDQ is used for the output driver 17 to output data. Because a circuit which does not perform full-swing, such as a stub series terminated transceiver logic (SSTL) interface which includes a termination for impedance matching, does not typically affect the operating characteristic of a memory chip, it is possible to decrease the level of the second external voltage VDDQ provided to the circuit.
In an I/O interface method where data is transmitted in synchronization with a clock signal frequency, such as in data transmission between a semiconductor memory device and a memory controller, as the load on a bus and a transmission frequency are increased it may be important for data to be accurately synchronized with a clock signal. Thus, the DLL circuit may be used to remove skew between an external clock signal and data output.
FIG. 3 is a block diagram showing a conventional DLL and output driver of a semiconductor memory device. As shown in FIG. 3, a DLL 50 according to the prior art includes an external clock signal input buffer 51, a phase detector 52, a low pass filter 53, a variable delay circuit 54, and a compensation delay circuit 55. The output driver 22 receives an internal clock signal from the DLL 50 through an internal clock signal buffer 24. The external clock signal input buffer 51 receives an external clock signal CLK_EX, and the phase detector 52 compares the phase of the external clock signal CLK_EX with the phase of an internal clock signal CLK2 and detects a phase error.
The low pass filter 53 controls a delay time of the variable delay circuit 54 by generating a control signal based on information on the phase error. The variable delay circuit 54 generates an internal clock signal CLK1 by delaying the external clock signal CLK_EX for a variable delay time in response to the control signal and locking the delayed external clock signal CLK_EX. The compensation delay circuit 55 delays the internal clock signal CLK1 for an output delay time tSAC and outputs the internal clock signal CLK2. The internal clock signal CLK2 is inputted to the phase detector 52 and is compared with the phase of the external clock signal CLK_EX.
The first external voltage VDD is supplied to the compensation delay circuit 55, and the second external voltage VDDQ is supplied to the output driver 22. The data output delay time tSAC is a time required to output data from the memory cell array 14 of FIG. 1 to outside the memory chip 20 through the output driver 22. In FIG. 3, “d1” denotes a delay time introduced by the external clock signal input buffer 51, and tCC−(d1+tSAC) denotes a delay time introduced by the variable delay circuit 54. Here, “tCC” denotes a period of the external clock signal CLK_EX.
In order to accurately detect a phase error between the external clock signal and the internal clock signal, the internal clock signal CLK1 is, typically, compensated for by the data output delay time tSAC. However, characteristics of the semiconductor memory device change with respect to changes in a manufacturing process, voltage, and temperature. The phase error due to changes in the characteristics of the semiconductor memory device is detected by the phase detector 52, and the delay time introduced by the variable delay circuit 54 may change accordingly. It is, typically, important for the delay time introduced by the variable delay circuit 54 to be accurately changed so as to generate an internal clock signal whose delay time is controlled based on the phase error due to the changes in the characteristics of the semiconductor memory device. However, it is also important for the data output delay time tSAC introduced by the compensation delay circuit 55 to be accurately compensated for.
In order to accurately compensate for the data output delay time tSAC, the compensation delay circuit 55 should be configured to introduce the same delay time as a delay time introduced by a real data path. However, it is very difficult to do this in practice. This is because the output driver 22 must be large so as to drive large loads outside the memory chip. Moreover, such large loads, typically, cannot be implemented inside the memory chip. In addition, in order to configure the compensation delay circuit 55 to have the same delay time as the delay time introduced by the output driver 22, it may be necessary to use the second external voltage VDDQ in the compensation delay circuit 55. However, since the second external voltage VDDQ may include a large amount of noise, it may have a detrimental influence on the operation of the DLL 50. Furthermore, if the compensation delay circuit 55 uses the second external voltage VDDQ as the operating voltage, a voltage level shifter may additionally be required for the DLL 50 using the first external voltage VDD. Therefore, it may be ineffective to use the second external voltage VDDQ in the compensation delay circuit 55. In addition, with respect to layout, because the second external voltage VDDQ is used only in the output driver 22, it may be necessary to form a pattern in another circuit layer.
FIG. 4 is a circuit diagram of the compensation delay circuit 55 of FIG. 3. The compensation delay circuit 55 of FIG. 4 uses only the first external voltage VDD as a power source. As shown in FIG. 4, the compensation delay circuit 55 includes a plurality of inverter circuits 61, 62, 63, and 64 that are consecutively connected with one another. The inverter circuits 61, 62, 63, and 64 are CMOS inverter circuits including PMOS transistors P1, P2, P3, and P4, and NMOS transistors N1, N2, N3, and N4.
The first external voltage VDD is supplied to the inverter circuits 61, 62, 63, and 64 as a supply voltage, and the internal clock signal CLK1 is inputted to the gates of the PMOS transistor P1 and the NMOS transistor N1. A delayed internal clock signal CLK2 is outputted from the drains of the PMOS transistor P4 and the NMOS transistor N4.
If information regarding changes of the second external voltage VDDQ is not reflected in the compensation delay circuit 55, it may not be possible to accurately compensate for the data output delay time tSAC when a potential difference occurs between the first external voltage VDD and the second external voltage VDDQ. More specifically, for example, both the first external voltage VDD and the second external voltage VDDQ may be 2.5V, and then only the second external voltage VDDQ may change to 2.7V the moment after the DLL 50 has completed locking. As the second external voltage VDDQ increases, the data output speed of the output driver 22 also increases. Thus, the data output delay time tSAC is reduced. However, since only the first external voltage VDD is supplied to the compensation delay circuit 55 of 2.5V, the delay time introduced by the compensation delay circuit 55 is longer than the data output delay time tSAC.
In contrast to the above, both the first external voltage VDD and the second external voltage VDDQ may be 2.5V, and then only the second external voltage VDDQ may change to 2.3V the moment after the DLL 50 has completed locking. In this case, the data output speed of the output driver 22 decreases, and thus the data output delay time tSAC is increased. However, since only the first external voltage VDD is supplied to the compensation delay circuit 55, a delay time introduced by the compensation delay circuit 55 is shorter than the data output delay time tSAC.